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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 3 1 publication order number: kaf?40000/d kaf-40000 7304 (h) x 5478 (v) full frame ccd image sensor description the kaf?40000 image sensor is a high performance, 40-megapixel ccd. based on the truesense 6.0 micron full frame ccd platform, the sensor features ultra-high resolution, broad dynamic range, and a four-output architecture. a lateral overflow drain suppresses image blooming, while an integrated pulse flush gate clears residual charge on the sensor with a single electrical pulse. a fast dump gate can be used to selectively remove a line of charge to facilitate partial image readout. the sensor also utilizes the truesense transparent gate electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. the sensor shares a common pin-out and electrical configuration with the kaf?50100 image sensor, allowing a single camera design to support both members of this sensor family. table 1. general specifications parameter typical value architecture full frame ccd (square pixels) total number of pixels 7410 (h) 5566 (v) = 41.2 mp number of effective pixels 7336 (h) 5510 (v) = 40.4 mp number of active pixels 7304 (h) 5478 (v) = 40.0 mp pixel size 6.0 m (h) 6.0 m (v) active image size 45.76 mm (h) 35.34 mm (v) 54.78 mm (diagonal), 645 1.3x optical format aspect ratio 4:3 horizontal outputs 4 saturation signal 42 ke ? output sensitivity 31 v/e ? quantum efficiency (peak r, g, b) 42%, 44%, 38% read noise (f = 18 mhz) 13 e ? dark signal (t = 60 c) 42 pa/cm 2 dark current doubling temperature 5.5 c dynamic range (f = 18 mhz) 70.2 db estimated linear dynamic range (f = 18 mhz) 69.3 db charge transfer efficiency horizontal vertical 0.999995 0.999999 blooming protection (4 ms exposure time) 1400x saturation exposure maximum date rate 18 mhz package ceramic pga cover glass mar coated, 2 sides note: all parameters are specified at t = 40 c unless otherwise noted. www.onsemi.com figure 1. kaf?40000 ccd image sensor features ? truesense transparent gate electrode for high sensitivity ? ultra-high resolution ? board dynamic range ? low noise architecture ? large active imaging area application ? digitization ? mapping/aerial ? photography see detailed ordering and shipping information on page 2 o f this data sheet. ordering information
kaf?40000 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kaf?40000?fxa?jd?aa gen2 color (bayer rgb), microlens, enhanced, esd, ceramic pga, clear cover glass with ar coating (both sides), standard grade kaf?40000?fx serial number kaf?40000?fxa?jd?ae gen2 color (bayer rgb), microlens, enhanced, esd, ceramic pga, clear cover glass with ar coating (both sides), engineering sample kaf?40000?cxa?jd?aa* gen1 color (bayer rgb), microlens, enhanced, esd, ceramic pga, clear cover glass with ar coating (both sides), standard grade kaf?40000?cx serial number kaf?40000?cxa?jd?ae* gen1 color (bayer rgb), microlens, enhanced, esd, ceramic pga, clear cover glass with ar coating (both sides), engineering sample *not recommended for new designs. see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kaf?40000 www.onsemi.com 3 device description architecture figure 2. block diagram 29 dark pixels 28 26 1 test row 4 4 1 test column 3652 vout la vsub og l h1 l rg l rd l v1 v2 fdg pfg 16 vdd la vss l 4 blue + 12 buffer pixels 16 16 16 28 h1a r 3716 pixels/line/output lod 4 4 1 test column 28 3652 4 1 4 10 1 16 28 4 1 4 10 1 3652 16 28 3652 4 1 4 10 1 16 28 4 1 4 10 1 vout lb vdd lb vout ra og r h1 r rg r rd r vdd ra vss r vout rb vdd rb h2 r h1b r h1a l h1b l h2 l (last vccd phase = v2) vsub v1 v2 fdg pfg lod xg kaf?40000 7304 (h) 5478 (v) 6.0 6.0 m pixels dark reference pixels surrounding the periphery of the device is a border of light shielded pixels creating a dark region. existing within this dark region are light shielded pixels that include 28 leading dark pixels on every line. there are also 29 full dark lines at the start and 26 full dark lines at the end of every frame. under normal circumstances, these pixels do not respond to light and may be used as a dark reference. dummy pixels within each horizontal shift register there are 20 leading pixels. these are designated as dummy pixels and should not be used to determine a dark reference level. these pixels are noted on the block diagram as the leading pixels in a horizontal line sequence: 1 + 10 + 4 + 1 (cte monitor pixel) + 4. active buffer pixels forming the outer boundary of the effective active pixel region, t here are 16 unshielded active buffer pixels between the photoactive area and the dark reference. these pixels are light sensitive but they are not tested for defects and non-uniformities. for the leading 16 active column pixels, the first 4 pixels are covered with blue pigment while the remaining active buffer pixels are arranged in a bayer pattern (r, gr, gb, b). cte monitor pixels two cte test columns, at the leading end of each output, and one cte test row are included for manufacturing test purposes. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs (charge) within the device. these photon-induced electrons are collected locally by the formation of potential wells at each pixel site. the number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. when the pixel?s capacity is reached, excess electrons are discharged into the lateral overflow drain (lod) to prevent crosstalk or ?blooming?. during the integration period, the v1 and v2 register clocks are held at a constant (low) level.
kaf?40000 www.onsemi.com 4 charge transport the integrated char ge from each pixel in the v ertical ccd (vccd) is transported to the output using a two-step process. each remaining line (row) of charge is first transported from the vccd to a dual parallel split horizontal register (hccd) using the v1 and v2 register clocks. the transfer to the hccd occurs on the falling edge of v2 while h1a is held high. this line of charge may be readout immediately (dual split) or may be passed through a transfer gate (xg) into a second (b) hccd register while the next line loads into the first (a) hccd register (dual parallel split). readout of each line in the hccd is always split at the middle and, thus, either two or four outputs are used. left (or right) outputs carry image content from pixels in the left (or right) columns of the vccd. a separate connection to the last h1 phase (h1l) is provided to improve the transfer speed of charge to the output amplifier. on each falling edge of h1l, a new charge packet is sensed by the output amplifier. left and right hccds are electrically isolated from each other except for the common transfer gate (xg). pulsed flush gate/fast dump gate the pulsed flush gate (pfg) feature is used to drain the charge of all pixels prior to exposure. the exception is pixels in the fast dump gate (fdg) row that are drained using the separate fdg pin. draining is accomplished by first clocking v2 high while v1 is held low . this forces all charge into the v2 phase of the pixel. while v2 is high, pfg (or fdg) may be clocked high to begin draining the signal from the pixel to the lod. charge transfer out of the pixel is fully completed only after v2 has been clocked low plus some characteristic time. horizontal register output structure the output consists of a floating diffusion connected to a three-stage source follower. charge presented to the floating diffusion (fd) is converted into a voltage and is current amplified in order to drive off-chip loads. the resulting voltage cha nge seen at the output is linearly related to the amount of charge placed on the fd. once the signal has been sampled by the system electronics, the reset gate (rg) is clocked to remove the signal and fd is reset to the potential applied by reset drain (rd). increased signal at the floating dif fusion reduces the voltage seen at the output pin. to activate the output structure, an off-chip current source must be added to the vout pin of the device. see figure 4. figure 3. output architecture (each output) hccd charge transfer source follower #1 source follower #2 source follower #3 floating diffusion h2 vdd vout h1 h2 hil og rg rd vsub vss
kaf?40000 www.onsemi.com 5 output load figure 4. recommended output structure load diagram 2n3904 or equivalent 0.1 f 1 k vout vdd = +15 v note: component values may be revised based on operating conditions and other design considerations. 140 buffered video output i out = |5 ma|
kaf?40000 www.onsemi.com 6 physical description pin description and device orientation figure 5. image transfer diagram viewed from the top (cover glass side) direction of transfer direction of transfer pin 1 to vout la to vout lb to vout ra to vout rb figure 6. pinout diagram 1. pins with the same name are nominally tied together on the circuit board and have the same operating conditions. in addition, pins l abeled with left (?l?) and (?r?) designations may also be tied together except for vout pins. 2. to achieve optimal output signal matching, electrical layout of the pcb should be made as symmetrical as possible relative to the left and right sides of the sensor. notes: 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 9 10 10 11 11 12 13 14 14 15 15 1 1 2 2 3 3 4 4 5 5 6 7 9 9 10 10 11 11 12 12 16 16 lod lod fdg v1 v1 v2 v2 lod vsub pfg v1 pfg v2 vsub vsub pfg pfg lod v2 v1 fdg vsub 8 8 a b c d a b c d 13 12 kaf?40000 vsub nc h1b r h1l r rg r og r vout rb vout ra h2 r h1a r vdd rb rd r vss r vdd ra vsub vsub xg h1b l h1l l rg l og l vout lb vout la h2 l h1a l vdd lb rd l vss l vdd la vsub
kaf?40000 www.onsemi.com 7 table 3. pin description pin name description a1 vsub substrate a2 vddla output amplifier supply, left a a3 vssl output amplifier return, left a4 rdl reset drain, left a5 vddlb output amplifier supply, left b a6 h1al horizontal phase 1, a left a7 h2l horizontal phase 2, left a10 h2r horizontal phase 2, right a11 h1ar horizontal phase 1, a right a12 vddrb output amplifier supply, right b a13 rdr reset drain, right a14 vssr output amplifier return, right a15 vddra output amplified supply, right a a16 vsub substrate b1 voutla video output, left a b2 voutlb video output, left b b3 ogl output gate, left b4 rgl reset gate, left b5 h1ll horizontal phase 1, last gate, left b6 h1bl horizontal phase 1, b left b7 xg horizontal transfer gate b8 vsub substrate b9 vsub substrate b10 nc no connection b11 h1br horizontal phase 1, b right b12 h1lr horizontal phase 1, last gate, right b13 rgr reset gate, right b14 ogr output gate, right b15 voutrb video output, right b b16 voutra video output, right a pin name description c1 lod lateral overflow drain c2 pfg pulse flush gate c3 v1 vertical phase 1 c4 v2 vertical phase 2 c5 pfg pulse flush gate c6 vsub substrate c7 vsub substrate c8 pfg pulse flush gate c9 v2 vertical phase 2 c10 v1 vertical phase 1 c11 pfg pulse flush gate c12 lod lateral overflow drain d1 vsub substrate d2 fdg fast dump gate d3 v1 vertical phase 1 d4 v2 vertical phase 2 d5 lod lateral overflow drain d8 lod lateral overflow drain d9 v2 vertical phase 2 d10 v1 vertical phase 1 d11 fdg fast dump gate d12 vsub substrate note: the leads are on a 0.100 spacing.
kaf?40000 www.onsemi.com 8 imaging performance table 4. typical operational conditions description test condition ? unless otherwise noted units notes readout time (t readout ) 2093 ms includes 140 overclock pixels includes 178 overclock lines integration time (t int ) variable 33 200 250 1000 ms low light tests saturation tests brightfield tests darkfield and linearity tests frame time (t readout + t int ) variable 2126 (2093 + 33) 2293 (2093 + 200) 2343 (2093 + 250) 3093 (2093 + 1000) ms low light tests saturation tests brightfield tests darkfield and linearity tests line time (t line ) 364.3 s includes 140 overclock pixels horizontal clock frequency 12 (as tested) mhz guaranteed for 18 mhz operation temperature ? room 20 c room temperature temperature ? device 29 c typical device operating temperature at test room temperature operation nominal operating levels dual parallel split mode table 5. specifications description symbol min. nom. max. units verification plan 15 saturation signal (note 1) n sat ne ? sat q/v 1075 1300 42 31 mv e ? v/e ? die photoresponse non-linearity (note 2) prnl 5 10 % die photoresponse non-uniformity (note 3) prnu 8.5 25 % p?p die readout dark signal (note 4) v dark,read 18 20 mv/s die integration dark signal (note 5) v dark,int 3 10 mv/s die dark signal non-uniformity (notes 6, 16) dsnu 1 4 mv p?p die dark signal doubling temperature (note 4) t 5.5 c design read noise (note 7) nr 13 e ? rms design dynamic range (note 8) dr 70.2 db design estimated linear dynamic range dr lin (est.) 69.3 db design red-green hue shift blue-green hue shift (note 9) rg hueunif bg hueunif 5 12 % die horizontal charge transfer efficiency (note 10) hcte 0.999995 die vertical charge transfer efficiency vcte 0.999999 0.999998 die blooming protection (note 11) x ab 800 1400 x e sat design dc offset, output amplifier (note 12) v odc 6.0 7.5 9.5 v die output amplifier bandwidth (note 13) f ?3db 220 mhz design output impedance, amplifier r out 100 145 300 die reset feedthrough v rft 0.5 v design
kaf?40000 www.onsemi.com 9 table 5. specifications (continued) description verification plan 15 units max. nom. min. symbol kaf?40000?fxa configuration gen2 color peak quantum efficiency red green blue qe max ? ? ? 39 45 37 ? ? ? % qe design peak quantum efficiency wavelength red green blue qe ? ? ? 600 530 470 ? ? ? nm design kaf?40000?cxa configuration gen1 color (note 17) peak quantum efficiency red green blue qe max ? ? ? 37 41 37 ? ? ? % qe design peak quantum efficiency wavelength red green blue qe ? ? ? 600 520 470 ? ? ? nm design 1. increasing output load currents to improve bandwidth will decrease these values. 2. worst-case deviation (from 15 mv & 90% n sat min) relative to a linear fit applied between 0 and 65% of v sat . 3. difference between the maximum and minimum average signal levels of 168 168 blocks within the sensor on a per color basis as a % of average signal level. 4. t = 60 c. t int = 0. average non-illuminated signal with respect to over-clocked horizontal register signal. 5. t = 60 c. average non-illuminated signal with respect to over-clocked vertical register signal. 6. t = 60 c. absolute difference between the maximum and minimum average signal levels of 168 168 blocks within the sensor. 7. rms deviation of horizontal over-clocked pixels measured in the dark. 8. 20log (ne ? sat / nr) 9. gradual variations in hue (red with respect to green pixels and blue with respect to green pixels) in regions of interest (16 8 168 blocks) within the sensor. the specification refers to the largest value of the response difference. 10. measured per transfer above and below (~70% v sat min) saturation exposure levels. typically, no degradation in hccd cte is observed up to 18 mhz. 11. x ab is the number of times above the v sat illumination level that the sensor will bloom by spot size doubling. the spot size is 10% of the imager height. x ab is measured at 4 ms. 12. video level offset with respect to ground. 13. last stage only. assumes 5 pf off-chip load. 14. amplitude of feed-through in vout during rg clocking. 15. a ?die? parameter is measured on every sensor during production testing. a ?design? parameter is quantified during design ve rification and not guaranteed by specification. 16. t int = 1000 ms. 17. this color filter set configuration (gen1) is not recommended for new designs.
kaf?40000 www.onsemi.com 10 typical performance curves figure 7. spectral response absolute quantum effeciency (%) kaf?40000 average quantum efficiency wavelength (nm) 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 5 10 15 20 25 30 35 40 45 50 figure 8. typical gr?gb qe difference qe response difference (gr?gb) kaf?40000 response difference (gr?gb) wavelength (nm)
kaf?40000 www.onsemi.com 11 figure 9. minimum expected anti-blooming performance kaf?40000 anti-blooming performance integration time (ms) 0 x ab 5 10152025 0 1000 2000 3000 4000 5000 6000
kaf?40000 www.onsemi.com 12 defect definitions operating conditions bright defect tests performed at t = 25 c, t int = 250 ms and t readout = 2093 ms. dark defect tests performed at t = 25 c, t int = 1,000 ms and t readout = 2093 ms. table 6. specifications classification points clusters single columns includes dead columns standard grade < 4,000 < 50 < 20 yes point defects a pixel that deviates by more than 36 mv above neighboring pixels under non-illuminated conditions. a pixel that deviates by more than 7% above or 11% below neighboring pixels under illuminated conditions cluster defect a grouping of not more than 10 adjacent point defects. cluster defects are separated by no less than 4 good pixels in any direction. column defect a grouping of more than 10 point defects along a single column. a column that deviates by more that 1.2 mv above neighboring columns under non-illuminated conditions. a column that deviates by more that 1.5% above or below neighboring columns under illuminated conditions. column defects are separated by no less than 4 good columns. no multiple column defects (double or more) will be permitted. column and cluster defects are separated by at least 4 good columns in the x direction. dead column a column that deviates by more than 50% below neighboring columns under illuminated conditions. saturated column a column that deviates by more than 120 mv above neighboring columns under non-illuminated conditions. no saturated columns are allowed.
kaf?40000 www.onsemi.com 13 operation table 7. absolute maximum ratings description symbol minimum maximum units diode pin voltages (notes 1, 2) v diode ?0.5 20 v gate pin voltages (notes 1, 3) v gate1 ?14.3 14.5 v rg pin voltage (note 1) v rg ?0.5 14.5 v overlapping gate voltages (note 4) v 1?2 ?14.3 14.5 v non-overlapping gate voltages (note 5) v q?q ?14.3 14.5 v output bias current (note 6) i out ?30 ma lod diode voltage (note 1) v lodt ?0.5 13.5 v operating temperature (note 7) t op 0 60 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. referenced to pin vsub. 2. includes pins: rd, vdd, vss, vout. 3. includes pins: v1, v2, h1a, h1b, h1l, h2, og, pfg, fdg, xg. 4. voltage dif ference between overlapping gates. includes: v1 to v2, h1/h1l to h2, h1l to og, v1 to h2, pfg to v1/v2, fdg to v1/ v2, xg to h1a/h1b/h2. 5. voltage difference between non-overlapping gates. includes: v1 to h1a/h1b/h1l, v2 to xg, h2 to pfg/fdg, pfg to fdg. 6. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher cu rrents and lower load capacitance at the expense of reduced gain (sensitivity). operation at these values will reduce mttf (mean time to f ailure). 7. noise performance will degrade at higher temperatures. power-up sequence the sequence chosen to perform an initial power-up is not critical for device reliability. a coordinated sequence may minimize noise and the following sequence is recommended: 1. connect the ground pins (vsub). 2. supply the appropriate biases and clocks to the remaining pins. table 8. dc bias operating conditions description symbol minimum nominal maximum units maximum dc current (ma) reset drain (note 1) v rd 11.3 11.5 11.7 v i rd = 0.01 output amplifier return (note 1) v ss 0.5 0.7 1.0 v i ss = 3.0 output amplifier supply (note 1) v dd 14.5 15.0 15.5 v i out + i ss substrate v sub 0 v 0.01 output gate (note 1) v og ?2.2 ?2.0 ?1.8 v 0.01 lateral drain (note 1) v lod 9.8 10.0 10.2 v 0.01 video output current (note 2) i out 5 10 ma 1. subscripts (l, r, la, lb, ra, rb, t, b) have not been included in the symbol list. 2. an output load sink must be applied to vout to activate output amplifier ? see figure 4.
kaf?40000 www.onsemi.com 14 ac operating conditions table 9. clock levels description symbol level minimum nominal maximum units v1 v1l low ?9.2 ?9.0 ?8.8 v v1h high 2.3 2.5 2.7 v v2 v2l low ?9.2 ?9.0 ?8.8 v v2h high 3.3 3.5 3.7 v h1a h1l low ?4.2 ?4.0 ?3.8 v h1h high 1.8 2.0 2.2 v h1b h1l low ?4.2 ?4.0 ?3.8 v h1h high 1.8 2.0 2.2 v h1l h1l low low ?6.2 ?6.0 ?5.8 v h1l high high 1.8 2.0 2.2 v h2 h2l low ?4.2 ?4.0 ?3.8 v h2h high 1.8 2.0 2.2 v rg vrgl low 0.8 1.0 1.2 v vrgh high 7.8 8.0 8.2 v pfg pfgl low ?9.2 ?9.0 ?8.8 v pfgh high 4.8 5.0 5.2 v fdg fdgl low ?9.2 ?9.0 ?8.8 v fdgh high 4.8 5.0 5.2 v xg xgl low ?4.7 ?4.5 ?4.3 v xgh high 2.8 3.0 3.2 v 1. subscripts (l, r) have not been included in this symbol column. 2. all pins draw less than 10 a dc current. capacitance values relative to sub (substrate). 3. capacitance values of left/right combined.
kaf?40000 www.onsemi.com 15 capacitance model figure 10. lumped capacitance value model ? kaf?40000 note: a simplified pin capacitance model is provided by on semiconductor as a guideline for circuit design and tends to overstate the effective capacitance experienced by the clock driver. this model should be used as a reference. although it is a moderately accurate target, it does not represent the values required for any automated circuit analysis. 258 nf pfg 439 pf h1a 7 pf vdd 455 nf v1 484 pf h1b 76 pf vss 517 nf v2 917 pf h2 rd 20 pf 16 pf lod 17 pf h1l rg 15 pf 120 pf fdg 237 pf xg 13 pf og 7 pf vout (each)
kaf?40000 www.onsemi.com 16 timing table 10. requirements and characteristics description symbol minimum nominal maximum units h1, h2 clock frequency (note 1, 2) f h 18 mhz v1, v2 clock frequency (note 1, 2) f v 25 khz v1?v2 cross-over v vcr 0 1.0 2.7 v h1?h2 cross-over v hcr ?2.0 ?1.0 0 v h1, h2 setup time t hs 5 s v2?h1a delay t d1 5 s h1a?xg delay t d2 30 s xg?v2 delay t d3 5 s h1, h2 rise, fall times (note 5, 6) t h1r , t h1f 5 10 % h1l rise ? h2 fall crossover (note 9) v h1lcr ?2.0 ?1.0 1.0 v v1, v2 rise, fall times (note 5) t v1r , t v1f 5 10 % rg clock pulse width (note 7) t rgw 5 ns rg rise, fall times (note 5) t rgr , t rgf 5 10 % v1, v2 clock pulse width (notes 2, 3, 4) t vw 16 20 s pixel period (1 count) (note 2) t e 55.56 ns h1l?vout delay t hv 10 ns rg?vout delay t rv 5 ns readout time (note 8) t readout ? ds t readout ? dps 1.35 0.76 s frame rate (note 8) t f ? ds t f ? dps 0.7 1.3 fps line rate (note 8) t lineds ? ds t linedp ? dps 242.2 274.4 s pfg holdoff time t pfg 180 s fdg holdoff time t fdg 20 s 1. 50% duty cycle values. 2. cte will degrade above the maximum frequency. 3. longer times will degrade noise performance. 4. measured where v clock is at 0 v. 5. relative to the pulse width (based on 50% of high/low levels). 6. the maximum specification or 10 ns whichever is greater based on the frequency of the horizontal clocks. 7. rg should be clocked continuously. 8. ds = dual split dps = dual parallel split. 9. the charge capacity near the output could be degraded if the voltage at the clock crossover point is outside this range.
kaf?40000 www.onsemi.com 17 edge alignment figure 11. timing edge alignment v hcr h2 l /h2 r v h1lcr h1a l /h1a r /h1b l /h1b r h2 l /h2 r h1l l /h1l r v vcr v1 v2 horizontal clock vertical clock
kaf?40000 www.onsemi.com 18 frame timing dual split timing reads the pixels out of voutla and voutra. h1b may be grounded in this operating mode. dual-parallel split timing reads pixels out of all four outputs with even lines reading out of voutla and voutra and odd lines reading out of voutlb and voutrb. figure 12. frame timing frame timing ? dual split frame timing ? dual-parallel split v1 v2 h1a/b/l h2 line 1 2 3 5565 5566 v1 v2 h1a h2 line pair 1 2 3 2782 2783 h1b/l xg xg t int t readout t int t readout frame timing detail figure 13. frame timing detail vertical clocks v1 high v1 low 10% 90% v1 t v t v1r t v1f v2 high v2 low 10% 90% v2 t v t v2r t v2f
kaf?40000 www.onsemi.com 19 line timing (each output) xg is held low unless the dual-parallel split timing is required. while operating in dual-parallel split mode, full resolution rows are passed from v2 (t d1 ), through h1a (t d2 ), and then passed through xg (t d3 ) and into h1b. during this time, a second, full resolution, row will load into h1a at the second falling edge of v2 following the characteristic delay t hd . figure 14. line timing line timing ? dual split line timing ? dual-parallel split v1 v2 h1a/b/l h2 v1 v2 h1a h2 h1b/l xg xg t v t v t hs 3716 cnts t v t v t v t v t hs 3716 cnts t d1 t d2 t d3 t line t line
kaf?40000 www.onsemi.com 20 pixel timing figure 15. pixel timing h1a/b/l h2 rg vout t e pixel timing detail figure 16. pixel timing detail t e / 2 t rgr t rgf 10% 90% rg low rg l /rg r v rg rg high reset clock t hr t hf 10% 90% h1a low / h1b low / h2 low 50% h1a high / h1b high / h2 high h1a r /h1b r /h2 r / h1a l /h1b l /h2 l t rgw t e / 2 t hr t hf 10% 90% h1l low 50% h1l high h1l r /h1l l horizontal clocks
kaf?40000 www.onsemi.com 21 mode of operation pulse flush gate timing the pfg clock resets all pixels in the array (except the fdg row). charge transfer out of the pixel is fully completed only after v2 has been clocked low as shown. figure 17. pulse flush gate timing v1 v2 pfg t flush t pfg t v t int t readout frame timing ? pulse flush operation fast dump gate (fdg) timing the fdg clock only resets pixels that happen to be in the fdg row. charge transfer out of the pixel is fully completed only after v2 has been clocked low plus the characteristic time period (t fdg ). the position of the fdg row is illustrated in figures 19?21, including the timing required for a simple 1 line dump operation. figure 18. fast line dump layout row# 4 3 2 1 fast dump gate row bottom lod contact row hccd register a hccd register b figure 19. one line dump timing example fdg v1 v2 h1 h2 3716 cnts t0 t5 t4 t3 t2 t1 t fdg line timing ? fast dump gate
kaf?40000 www.onsemi.com 22 figure 20. line dump timing example t fdg 3716 cnts v1 v2 h2 h1 fdg t v t v line timing ? fast dump gate (3 line dump) figure 21. one line dump pixel illustration using color filter designation hccd b v2 hccd a xg v2 v1 4 vccd fdg lod 4 3 2 1 v2 v1 v2 v1 v2 v1 v2 v1 t0 gr4 b4 gr4 gr2 gr2 b2 r3 gb3 b4 r3 gb3 r1 gb1 r1 gb1 b2 gr4 b4 gr4 b4 r3 gb3 r3 gb3 gr2 b2 gr2 b2 r1 gb1 r1 gb1 t1 gr4 b4 gr4 b4 r3 gb3 r1 gb1 r1 gb1 t2 r3 gb3 gr4 b4 gr4 b4 r3 gb3 r3 gb3 r1 gb1 r1 gb1 t3 gr4 b4 gr4 b4 r3 gb3 r3 gb3 r1 gb1 r1 gb1 t4 r1 gb1 r1 gb1 gr4 b4 gr4 b4 r3 gb3 r3 gb3 t5 note: areas highlighted in yellow represent pixels drained of charge.
kaf?40000 www.onsemi.com 23 storage and handling table 11. storage conditions description symbol minimum maximum units storage temperature (note 1) t st ?20 70 c 1. long-term storage toward the maximum temperature will accelerate color filter degradation. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kaf?40000 www.onsemi.com 24 mechanical drawings completed assembly figure 22. completed assembly drawing
kaf?40000 www.onsemi.com 25 alignment marks the 98 + 48 mark should be used if alignment to die surface is required. figure 23. individual alignment mark ?98 + 48? (1 of 4) figure 24. location of recommended alignment marks (4 locations) 4 3 1 2 1 2 3 4 x?y: die center diagonal: image center note: image center is ?0.55 m (x) and 34.05 m (y) from die center.
kaf?40000 www.onsemi.com 26 locations of marked alignment marks are listed in the table below with respect to the die center. locations are listed in m from the die center. table 12. alignment mark x location y location 1 ?22700 ?16340 2 ?22700 16340 3 22700 16340 4 22700 ?16340 locations of marked alignment marks are listed in the table below with respect to the image center. locations are listed in m from the image center. table 13. alignment mark x location y location 1 ?22699.45 ?16374.05 2 ?22699.45 16305.95 3 22700.55 16305.95 4 22700.55 ?16374.05 cover glass specification 1. substrate material schott d263t eco or equivalent. 2. 10 m max. scratch/dig specification on the glass. no defect in the glass that exceeds 10 m in any x?y dimension. 3. multilayer anti-reflective coating. table 14. wavelength total reflectance 420?450 2% 450?630 1% 630?680 2% on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kaf?40000/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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